| 摘要 |
PURPOSE:To realize a semiconductor device with its ON resistance lower and switching speed higher by a method wherein the width of a channel region is narrowed. CONSTITUTION:On a low-temperature N-layer 2 covering a semiconductor substrate N<+>-layer 1, an SiO2 insulating films 5a, 5b, polycrystalline silicon layer 6 for electrodes, CVD-SiO2 layer 5C are formed by deposition, in that order. A photoresist 7 is formed thereon, wherewith the polycrystalline silicon layer 6 is patterned, which is followed by the implantation of P<+>-type impurity ions. A process follows wherein the photoresist 7 is removed, heating is accomplished for the formation of a P<+>-type layer 3b, and then low-temperature P-type impurity ions 4a are implanted. The pattern of the CVD-SiO2 layer 5C is removed, and thermal diffusion is accomplished for the formation of a P-layer 4b for a channel region. After this, a source N<+>-type region is formed by means of ion implantation, a CVD-SiO2 layer 5d is deposited, heat treatment is accomplished and, finally, a contact hole is provided for the construction of an Al electrode 9. |
