| 摘要 |
PURPOSE:To prevent the titled device from enlarging in size of the system and to make correspondence between the multiplex-line channel number and the line number of each line by concentrating the real-data-speed information and the line number of each individual line, and putting the result in the channel memory to rewrite the content of the said channel memory. CONSTITUTION:Among the data that are read out from a channel memory 7, LN is the address signal to a multiplexing circuit 11. The data from a register 19 of the individual line block B1 corresponding to the specified LN=1, is outputted to a multiplex signal line S11. At the same time, the LN is an address signal to a separating circuit 9, and one signal line among the lines S91-SR2 becomes '1' in correspondence to its specified LN. As to an FIFO memory 16 on the reception side, the input signal 17 sequentially written by an input clock signal 18 is read out sequentially in time proportion, transmitted to the multiplexing circuit 11, and multiplexed to 64kbps. And further, LN, DSR, and (RCNT+1) are written in the channel memory 7. As a result, the correspondence between the channel number of the multiplex line and the line number of each individual line can be optionally modified, and the enlargement of the system in size is prevented. |
