发明名称 MOS I/O PROTECTION CIRCUIT
摘要 PURPOSE:To obtain the titled device which can realize high electrostatic withstand voltage without needing excessive pattern areas, by a method wherein an I/O protection silicon resistor is arranged immediately under a bonding pad. CONSTITUTION:Most of a poly Si resistor 2 is provided immediately under the bonding pad 1, and partly extended to the outside of immediately under the bonding pad 1. An insulation film is interposed between the bonding pad 1 and the poly Si resistor 2. The resistor 2 is electrically connected to the bonding pad 1 through an aperture 11 and electrically connected through an aperture 12 to a conductor 13 connected to an inner circuit and a protection diode or protection transistor. The poly Si resistor 2 clamps the abnormal high voltage impressed from outside on the bonding pad 1 and thus protects the gate insulation film of the inner circuit, particularly, a MOS transistor from high voltage. This construction saves the area required for the I/O protection circuit.
申请公布号 JPS61156852(A) 申请公布日期 1986.07.16
申请号 JP19840276164 申请日期 1984.12.28
申请人 TOSHIBA CORP 发明人 SHIMAMUNE YUJI
分类号 H01L29/78;H01L27/02;H01L27/06 主分类号 H01L29/78
代理机构 代理人
主权项
地址