| 摘要 |
PURPOSE:To attain a full-speed operation of a parallel multiplier without rate- determining the speed of a basic cell array part, by connecting a CLA (carry look ahead) adder of 2 bits in series to the lowest bit part of each basic cell train. CONSTITUTION:A carry output signal 13, a signal 14 of the encoder output of a booth having a multiplier Y and the sum output 15 of basic cells (j, 0) are serve as the lower digit inputs of a CLA adder of 2 bits. While the carry output 16 of the basic cells (j, 0) and the sum output 17 of basic ells (j, 1) serve as the upper digit inputs of the adder 12. The sum output 19 of an LSB and the sum output 20 of an MSB serve as the corresponding lower products Pi and Pi+1 among the carry output 18 of the adder 12, the output 19 in the 2-bit sum output and the output 20. The output 18 of the adder 12 is supplied in series to the carry input terminal of the adder 12 of the next stage. |
