发明名称 |
Balanced full adder circuit. |
摘要 |
<p>A full adder circuit includes a sum circuit section, a carry-out circuit section, a carry-in circuit section; and an output circuit section. The sum circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The sum circuit section also includes a plurality of N-channel type of MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order. The carry-out circuit section includes a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement binary addend signals of an ith order. The carry-out circuit section also includes a plurality of N-channel MOS transistors having their gates adapted to receive true and complement binary augend signals of an ith order. The carry-in circuit section is formed of a plurality of N-channel type MOS transistors having their gates adapted to receive true and complement carry-in signals of an ith-1 order. The output circuit section includes a first pair of cross-coupled P-channel type MOS transistors connected to the sum circuit section and having their drains connected to respective true and complement sum output terminals. The output circuit section further includes a second pair of cross-coupled P-channel type MOS tansistors connected to the carry-out circuit section and having their drains connected to respective true and complement carry-out terminals. All of the transistors are arranged on an integrated circuit substrate with topological regularity.</p> |
申请公布号 |
EP0187698(A2) |
申请公布日期 |
1986.07.16 |
申请号 |
EP19860300026 |
申请日期 |
1986.01.03 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
FANG, SHENG |
分类号 |
G06F7/50;G06F7/501;G06F7/506 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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