| 摘要 |
<p>A system for controlling the transfer of commands between processors of a multiprocessor system, including a single control unit connected to all the processors by separate information transfer lines. The control unit selects the processor generating a command transfer request signal in a predetermined priority order and receives the processor address from the selected processor. The receiving processor and predetermined transfer information are determined in accordance with the selected processor, the processor address, and the processor status information determined by the processor address. The predetermined transfer information is transferred to the receiving processor via an information transfer path established between the selected processor and the receiving processor.</p> |
