| 摘要 |
<p>A personal computer is disclosed having a high speed microprocessor which executes in either a FAST mode or a SLOW mode application programs written for a slow speed microprocessor. The slow speed microprocessor contains a pre-fetch queue that is smaller than the pre-fetch queue of the high speed microprocessor. A logic means is included, responsive to a mode select signal for controlling the wait state of said high speed microprocessor when in the SLOW speed mode so that every other word accessed to said RAM memory requires two consecutive word accesses to the same memory address to obtain the contents of the addressed location thereby enabling said high speed microprocessor to execute application programs in the SLOW mode, on the average, at substantially the same speed as the program normally runs on the slow speed microprocessor.</p> |
