| 摘要 |
PURPOSE:To decrease an error of an integration value of a frequency division signal even when a power failure takes place by providing the 1st frequency division circuit obtaining a frequency division output when a half of the count is counted and the 2nd frequency division circuit causing the same frequency division output state with the input of a reset signal the same as the reception of the 1st frequency division output. CONSTITUTION:When a measurement signal S is inputted, a 2/8 frequency division circuit 10 outputs one pulse every time 4 pulses of the signal S are counted and a frequency division output B1 is obtained. When the frequency division output is inputted to a 1/2 frequency division circuit 11, a frequency division output B2 is obtained. During the frequency division, when a power failure takes place at a time t1 and power is applied again at a time t2, a reset signal R is inputted at the time t2. Thus, the frequency division output state of the circuit 10 is brought forcibly to a high level, that is, the frequency division output as a time (time tc) when a half of 8 pulses of the measuring signal S is counted. Further, the frequency division state of the 1/2 frequency division circuit 11 is made identical to the frequency division output state receiving the frequency division output B1 at a time (time tc) when the circuit 10 counts 4 pulses. Thus, in the operation after power reapplication, the measuring signal S undergoes frequency division so that four pulses of the signal S are counted. |
