发明名称 SIGNAL TRANSMISSION LINE OF SEMICONDUCTOR IC
摘要 PURPOSE:To speed up signal transmission of the titled device by reducing the parasitic capacitance of signal wirings, by a method wherein signal wirings are arranged into adjacent wirings with required wiring gaps and steps. CONSTITUTION:Metallic wirings 12, 13 of the first layer and a signal wiring 14 as the metallic wiring of the second layer are formed on a substrate 11 via insulation film. The wirings 12, 13 are provided in parallel with the wiring 14 by having a step. The signal wiring 14 is formed while keeping the horizontal distances (x) between itself and the adjacent wirings 12, 13 equal to the wiring width (d) of the signal wiring 14 or greater than this. Since this construction of the signal wiring line enlarges the gap between the wiring 14 and the substrate 11, the to-substrate capacitance C1' reduces. Since the wiring 14 and the adjacent wirings 12, 13 have steps in the longitudinal direction, the wiring capacitance C2' reduces, and the parasitic capacitance C1'+C2' largely reduces.
申请公布号 JPS61156834(A) 申请公布日期 1986.07.16
申请号 JP19840276131 申请日期 1984.12.28
申请人 TOSHIBA CORP 发明人 YASUDA YOJI
分类号 H01L21/768;G11C11/401;H01L23/522;(IPC1-7):H01L21/88 主分类号 H01L21/768
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