| 摘要 |
PURPOSE:To improve a data transfer efficiency between a main memory and a peripheral control device by providing a temporary memory means to buffer a data transfer and a means to store the condition information, deciding the condition information, and controlling generate a transfer request signal only when the data can be transferred. CONSTITUTION:In case of the writing by a DMA, namely, the transfer from a main memory to a memory 50 for display, an instruction only for the DMA writing from a CPU10 to a display controller 40 is transferred to the writing FIFO4021. At a processor 401, the instruction in the writing FIFO is removed and decoded, and the processing of a DMA writing is executed. After the number of transfer words is counted and placed at a transfer counter 405 as pretreatment of the DMA writing, starting is loaded to a DMA signal control circuit 404. At a DMA signal control circuit 404, an FIFO condition flag is referred, the vacancy is present, and then, a DMA transfer request signal is generated. A DMA controller 30 obtains the control right of the system bus and controls the DMA transfer in accordance with the prescribed action mode.
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