发明名称 RESET ADDRESS GENERATING CIRCUIT
摘要 PURPOSE:To deliver a different answer in a manual resetting mode after application of a power supply by securing a setting-enable state for the reset signal when a power supply is applied with operation of a switch provided to a memory and also through a data bus of a microprocessor. CONSTITUTION:When a power supply is applied, a memory address signal of a system start program is set to a flip-flop 10 by an initial reset signal IZ and in the ON/OFF states of a switch 12. While an MPU2 jumps to a reset address and supplies a reset address signal CS and a read signal RD. Thus the memory address signal of the system start program set to a reset address generating circuit 1 by the switch 12 is transferred to the MPU2 via a gate 11 and executed. Then a manual reset signal MRST is produced and the MPU2 jumps again to the reset address. Thus a reset address different from that obtained in an application mode of the power supply is outputted from the circuit 1.
申请公布号 JPS61156336(A) 申请公布日期 1986.07.16
申请号 JP19840281344 申请日期 1984.12.27
申请人 MEIDENSHA ELECTRIC MFG CO LTD 发明人 KATSUMATA NORIAKI
分类号 G06F11/14;G06F1/00;G06F1/24;G06F9/06;G06F9/46;G06F9/48;G06F11/00 主分类号 G06F11/14
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