发明名称 TLB PURGE CONTROL SYSTEM
摘要 PURPOSE:To improve an execution speed of a TLB partial purge instruction and to improve the whole information processing efficiency by constituting so that an identifier can be part of a TLB address, changing the value of an identifying bit at the time of starting a TLB and limiting the TLB address to an address covering are (VM area). CONSTITUTION:A TLB address of a TLB.AR11 is counted up starting from '0' by '1' by the counter construction of the identifier bit and an address field 13, and then, a TLB purge is first executed in an HYP area 17. Not to execute the meaningless purge, when the TLB purge is started, the value of an identifier bit 12 is set to all '0', namely, from '00' to '1', namely, to '01'. In such a way, by the counter construction of the address of the TLB.AR11, the TLB purge is started from the area, where two high-order bits of the address are '01', namely, the first address position of a VM area 18, and the purge to the HYP area 17 is not executed.
申请公布号 JPS61156445(A) 申请公布日期 1986.07.16
申请号 JP19840276351 申请日期 1984.12.28
申请人 FUJITSU LTD 发明人 FUJIMAKI HIDEAKI;TSUJITA HIROYUKI
分类号 G06F12/10 主分类号 G06F12/10
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