| 摘要 |
PURPOSE:To obtain a PLL synchronization detecting circuit having a clock detecting circuit suitable for an integration and providing a loop filter change- over switch being controlled by an output of a level detecting circuit and for changing-over a loop filter interposed in the PLL circuit. CONSTITUTION:An output signal of an image detecting circuit 9 is amplified in an image amplifying circuit 10 and an output dynamic range is not an object with respect to a carrier zero level. In a first level comparison circuit 11 composed of transistors TRQ29-Q31 and resistances R28-R35, repetition signals of voltages VL, VH are obtained through an emitter follower constituted by a TRQ 31. This comparison output is transmitted to an LPF 12 composed of the resistance 34 and a capacitor C2, smoothed and given to a second level comparison circuit and a loop filter changer-over circuit switch 13 to turn off the switch 13. When a PLL circuit is in a condition of a clock, in the output of the circuit 10, an image signal wave shape in which a signal exists at a lower side from the carrier zero level and the switch is turned ON.
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