发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To prevent the occurrence of latch up, by providing the first conducting type diffused layer, which is connected to a substrate potential between an island region and a protecting island region. CONSTITUTION:A P-type island region 2 is formed on an N-type substrate 1. In this island region 2, the following layers are formed: a P-type diffused layer 3, which fixes the island region 2 at a ground potential; an N-type diffused layer 4, which is connected to an input pad; and an N-type diffused layer 5 at the ground potential. An N-type diffused layer 6 for fixing a substrate potential and a P-type fidiffused layer 7 at the substrate potential are provided in the vicinity of the island region 2. A cut layer 8 is formed between the island region 2 and the P-type diffused layer 7. An N-type diffused layer 10 at the substrate potential is formed between the cut layer 8 and the island region 2. Electrons are implanted through the N-type diffused layer 4 and reach the N-type substrate. Of these electrons, the electrons, whose path to the N-type diffused layer is shielded by the cut layer 8, can be positively absorbed by the N-type diffused layer 10. The decrease in potential in the vicinity of the P-type diffused region is drastically suppressed. Therefore, the turning-ON of a lateral P-N-P transistor can be prevented.
申请公布号 JPS61154158(A) 申请公布日期 1986.07.12
申请号 JP19840277344 申请日期 1984.12.27
申请人 NEC CORP 发明人 HINOOKA KIYONOBU
分类号 H01L27/08;H01L27/092 主分类号 H01L27/08
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