| 摘要 |
<p>PURPOSE:To shorten the time from the sampling of the external signal to the determination of the internal signal without fastening a clock frequency and to prevent the output of a middle value when a non-synchronizing signal is synchronized by providing plural latch circuits. CONSTITUTION:FF102-105 constitutes the first - the fourth latch circuits to transfer input data D to an output terminal Q when a control signal input C is asserted, and to hold and output an output signal Q when the input is negated. An input signal 110 inputted from an input signal 101 is latched to an FF102 by a timing clock phi1, and the output signal 120 is latched again to FF103 by a clock phi2 dislocated to 90 deg. from the clock phi1. Thus, a non- synchronizing signal is sampled by a tailing edge of the clock phi1 through FF102-FF105, and the effective value can be outputted from the tailing edge of the clock phi2. Thus, the non-synchronizing signal can be synchronized at a high speed and at the time of synchronization, the middle value can not be outputted.</p> |
