发明名称 DIVIDING CIRCUIT
摘要 PURPOSE:To improve the utility of hardware by using a multiplier/divider circuit in common under the condition that a dividend is divided by a divisor and the divisor is an odd number to execute the division in the same degree of speed as that of a multiplication. CONSTITUTION:A divisor X being an odd number and a Y being a quotient are given, the Y is taken as an unknown number and the Y expressed from Z=XY is obtained by using a multiplier circuit. Thus, -Z is given to an input (a) of the multiplier circuit and the X is given to an input (x), and each bit of the Y connected to the input (y) is selected so that the product sum s=-Z+XY is zero. According to the expression of 1's complement, a negative number is expressed by bit inversion. Then -Z is obtained by applying inversion to each bit of the Z. Further, in the expression of 1's complement, 0 has two expressions of all bit 0 and all bit 1, but in this case, a negative number and a positive number are added, then 0 is expressed in all bit 1. That is, each bit of the Y is selected so that the output of a multiplier circuit is all bit 1.
申请公布号 JPS61151739(A) 申请公布日期 1986.07.10
申请号 JP19840273212 申请日期 1984.12.26
申请人 TOSHIBA CORP 发明人 NAKAMURA SADAO
分类号 G06F7/537;G06F7/506;G06F7/52;G06F7/53;G06F7/535 主分类号 G06F7/537
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