| 摘要 |
PURPOSE:To lower ON resistance characteristics effectively by forming N<+> layers at predetermined positions in a pair of P layers shaped to an N-type Si substrate at regular intervals and N<+> depletion-layer preventing regions surrounding the P layers while being brought into contact with the P layers. CONSTITUTION:P layers 11 are shaped to an Si substrate, in which an N<-> layer 10b is superposed to an N<-> layer 10a, at a regular interval, and surrounded by N<+> depletion-layer preventive regions 12 while being fast stuck to the regions 12. N<+> layers 13 as sources are formed into the P layers 11 at regular intervals. An SiO2 layer 14 is shaped to the main surface of the N<-> layer 10b, windows are bored and source electrodes 15 connecting the N<+> layers 13 are attached, and a gate electrode 16 is buried to the SiO2 14 on a narrow region 18 between the P layers 11. A drain electrode is attached to the N<+> layer 10a. Impurity concentration in each layer is set in order of the N<+> layers 13 > the P layer 11 > the depletion-layer preventive region 12 > the N<-> layer 10a. According to the constitution, depletion layers can be inhibited in the interface regions of bases/drains on ON operation, and the increase of the spreading resistance of the narrow region 18 can be reduced.
|
