| 摘要 |
<p>A memory array is provided which includes a common sense line (SL) to which is connected first and second series of cells, each cell of each series includes a storage capacitor (C), switching means (T) and a bit line (BL) connected to a plate of the storage capacitor (C), with a common word line (WL) connected to the control electrodes of each of the switching means. The switching means, preferably field effect transistors, of each series of cells have progressively higher threshold voltages beginning at the sense line, and the voltage applied to the common word line has a magnitude greater than that of the highest threshold voltage. Data is stored into or read from the storage capacitors by selecting the common word line and the bit line of the desired cell in a sequential manner.</p> |
