发明名称 SEMICONDUCTOR INTEGRATED LOGIC CIRCUIT
摘要 PURPOSE:To soften the transient current of an output buffer circuit by providing a driving circuit having one input and plural outputs which are equivalent logically, respectively, connecting the output of this driving circuit to the base of plural NPNTrs which are different from each other, and connecting in common the collectors of said Trs. CONSTITUTION:A TrQ1 being a driving circuit is operated as a phase split stage Tr. Also, capacitors C11, C12 and C13 being delaying circuits having each different delay time have each different capacity. Therefore, a base current flowing into Trs Q21, Q22 and Q23 is delayed by the relative value of delay quantities T1, T2 of the figure, and a corresponding shift is generated in the operation timing of the output Trs Q21, Q22 and Q23. A current waveform shown in the figure is that of the case when a current which is charged to a load capacity C1 is discharged by the Trs Q21, Q22 and Q23, and a composite current ISIGMA shows a current waveform flowing into a ground line. In such a way, the rise transient waveform of each current of the figure is much gentler than a conventional one.
申请公布号 JPS61150519(A) 申请公布日期 1986.07.09
申请号 JP19840278011 申请日期 1984.12.25
申请人 NEC CORP 发明人 MABUCHI YOSHIHIRO
分类号 H03K19/018;H03K17/16;H03K19/003 主分类号 H03K19/018
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