发明名称 MANUFACTURE OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To obtain a complementary type FET simply by forming a P layer and an N layer to the surface of a semi-insulating compound semiconductor, attaching a gate electrode and source-drain electrodes to each of the layers by an impurity, through which the P layer is changed into an N type, and thermally treating the whole. CONSTITUTION:An N layer 11 and a P layer 21 are formed to a semi-insulating GaAs substrate 1. A gate electrode 25a to the P layer 21 in the two layer constitution of a material AuGe.Au containing Ge, through which the P layer is converted into an N type, and a source electrode 13 and a drain electrode 14 to the N layer 11 are shaped simultaneously. Ge is diffused to a junction section in the electrode 25a through heat treatment to form an N type gate 22a while junction sections in the electrodes 13, 14 are alloyed to shape P-N junctions and ohmic connections. A gate electrode 15a is attached onto the N layer in the two layer constitution of AuZn.Au containing Zn, through which the N layer 11 is converted into a P type, and source-drain electrodes 23, 24 to the P layer 21, heat treatment for the time shorter than the last time at a temperature lower than the last time is executed, an adverse effect on the gate 22a is avoided, and lastly wirings 2 are wired, thus manufacturing a complementary type circuit. According to the method, a gate and the gate electrode need not be positioned, and man-hours required are reduced.
申请公布号 JPS61150380(A) 申请公布日期 1986.07.09
申请号 JP19840276024 申请日期 1984.12.25
申请人 FUJITSU LTD 发明人 NAKAYAMA YOSHIRO
分类号 H01L29/808;H01L21/337;H01L21/8222;H01L21/8252;H01L27/082 主分类号 H01L29/808
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