| 摘要 |
PURPOSE:To shorten the time that the input of power generated at synchronizing time is zero by outputting a frequency converter gate block signal delayed by a synchronizing signal. CONSTITUTION:When a synchronous motor 4 is started, a switch 6, 7 are closed to start synchronizing at low frequency using a frequency converter 3. A synchronization detector 11 outputs the synchronizing signal A of a switch 8 when the voltage V1 of an AC power bus 1 and the voltage, frequency and phase of the terminal voltage V2 of a motor 4 fall within the prescribed difference. A time delay circuit 12 outputs the gate block signal of the converter 3 after the delay within time (T1-T0) from the signal A. Here, T1 is a time required for closing the switch 8, and T1 is a time required for a gate block. Thus, when the motors are synchronized, it can prevent a rush current from flowing to the motors. |
