| 摘要 |
PURPOSE:To reduce the (hfe) dependency of an output potential, and suppressing small a variation in an H level by providing an output potential compensating circuit on an output stage of an Emitter Coupled Logic (ECL) logical circuit. CONSTITUTION:An output potential compensating circuit 1 is constituted of a compensating transistor Tr3 which has connected the collector to a common contact of the collector of an input transistor Tr1 and the base of an output transistor Tr0, and has connected the emitter to the second power source VEE, and a resistance or a constant-current source IBC which has been connected between the base of the transistor Tr3 and the first power source VCC. In such an constitution, when a collector current of the transistor Tr3 is denoted as ICTr3, a relation to the constant-current IBC is shown by ICTr3=IBC.hfe. In this case, the (HFE) is a current amplification factor of the transistor Tr3. It is understood that when the (hfe) of the transistor Tr3 becomes small, the collector current ICTr3 becomes small. In this way, as the (hfe) is varied, IBTr0 and ICTr3 increase or decrease in each opposite direction.
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