发明名称 INTERRUPTION CONTROL CIRCUIT
摘要 PURPOSE:To share the terminal of an interruption factor input by detecting an interruption factor in timing corresponding to each CPU based on the value of a specifying flag and distributing an interruption request signal to plural CPUs. CONSTITUTION:When the value of the specifying flat 4 is '1', the interruption factor inputted from the terminal 1 turns out to be the output signal 6 of a gate 5 as it is in the timing T1. Receiving this signal, an interruption detecting part 7 detects the occurrence of the interruption, and outputs an interruption request signal 8. In the timing T1 the request signal 8 is transmitted to the CPU2, which enters the interruption processing. Provided that the gate 5 will not be opened in the timing T2, because the value of the specifying flag 4 is '1', and the interruption factor is not transmitted to the interruption detecting part, whereby the CPU3 will not be interrupted. On the other hand, when the value of the specifying flat is '0', the inteeruption factor is detected in the timing T2, and the interruption request signal 8 is transmitted to the CPU3, whereby the terminal 1 functions as the terminal of the interruption factor input of the CPU3.
申请公布号 JPS61150062(A) 申请公布日期 1986.07.08
申请号 JP19840277134 申请日期 1984.12.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 FUJIOKA EMI;SUZUKI TOSHIAKI;MATSUZAKI TOSHIMICHI;SAKAO TAKASHI
分类号 G06F9/46;G06F15/16;G06F15/17;G06F15/177 主分类号 G06F9/46
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