| 摘要 |
PURPOSE:To lighten a burden of a central processor, and to improve the whole throughput by reconstituting dynamically a memory accessible area. CONSTITUTION:A write address counter 101 and a read address counter 102 of a circuit of a storage device having a memory circuit 109 and its memory controlling circuit loads information on data buses D0-D7, through a bidirectional bus driver 113 to a designated address in the memory circuit 109, when writing a data, and loads data which has been read out of its address, onto the data buses D0-D7 through the bidirectional bus driver 113, when read ing out the data. Also, from a CPU, a write signal, a readout signal, chip selecting signals CS0-CS7, and the data buses D0-D7 are connected. In this way, in accordance with a result of comparison of an address in an area with a prescribed address of the area, the area is reconstituted.
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