| 摘要 |
<p>PURPOSE:To continuously read and write in a pile line type at a cycle time of high speed equal to a delay time for one circuit block by providing a temporary memory circuit in respective circuit blocks and operating it synchronously with a clock pulse. CONSTITUTION:Temporary memory circuits 6-8 synchronously operate according to a clock pulse C. As for the temporary memory circuits 6-8, it is necessary to select the circuit small in a propagation delay time tp and small in a circuit scale and consumed power and it is desired to change over and use a function for temporarily storing a signal and a function for not storing the input signal and passing as it is. As the temporary memory circuit satisfying these conditions, there is a latch circuit based on a D type flip-flop. Since a memory signal M is read every clock cycle Tc by one, a reading cycle time trc' in this case is equal to the clock cycle Tc. The clock cycle Tc may preferably coincide with the longest time of delay times of the respective circuits.</p> |
