| 摘要 |
PURPOSE:To attain high stable frame synchronization by transmitting alternately two kinds of frame synchronizing data with different bit patterns at each frame and taking it as the frame synchronization state when one received frame is synchronized. CONSTITUTION:Reception data fed to an input terminal IN is inputted to a bit synchronizing circuit 1, where a bit clock pulse BTCK is recovered. Two kinks of frame synchronizing data AS, BS having different patterns are arranged alternately at each frame in the reception data, and the synchronizing data AS, BS are detected in synchronization with the BTCK by frame synchronizing pattern detection circuits 2, 3 for words A, B. The pulse BTCK is counted by a bit counter 4, from which frame pulses AFSYNC and BFSYNC whose phases are shifted by 180 deg. at two frame interval are generated and the phase is discriminated with the output of the circuits 2, 3 by phase coincidence discrimination circuits 5, 6 respectively, and when any frame is synchronized, the counter 4 is not initialized and a frame synchronizing signal is outputted from a gate 10. |
