发明名称 MEMORY CONTROL DEVICE
摘要 <p>PURPOSE:To reduce remarkably the power consumption of a queued memory circuit by providing a means for generating and stopping memory timing of a random access memory elememt. CONSTITUTION:A clock generator 103 has a reference clock generating source of XTAL, etc., generates a clock and drives a timing generator through a gate 104. One input of the gate 104 is a signal STOP which comes from a CPU 110, and when this STOP is ''1'', the gate 104 is not opened, therefore, the timing generator cannot generate timing of RAS, CAS, WE, etc. Also, at that time, a refresh operation is also stopped. In case when a memory element of a memory circuit 130 is a DRAM especially, the largest power is consumed at the time of the refresh operation, therefore, a stop of the refresh operation is useful for reducing the power consumptiom.</p>
申请公布号 JPS61148544(A) 申请公布日期 1986.07.07
申请号 JP19840271047 申请日期 1984.12.24
申请人 CANON INC 发明人 OGATA YUKIHIKO
分类号 G06F1/26;G06F1/00;G06F1/04;G06F12/00;G06F12/06;G11C7/00;G11C11/405;G11C11/406 主分类号 G06F1/26
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