| 摘要 |
<p>PURPOSE:To attain accurate signal processing by shifting its capture range to a proper section in response to a reproducing signal at a PLL extracting a clock signal so as to obtain the clock signal in synchronizing with an input signal at all times. CONSTITUTION:A deciding circuit 47 detects only a period when a pilot signal is reproduced by a signal from a pulse generator 23, applies decision for the period only, and the frequency dividing ratio of a frequency divider 43 is controlled from the result of decision. When the frequency of the reproduced pilot signal is f0/4 (bit rate of an NRZ signal is fCH/2), the frequency of the pilot signal at recording is f0/2, the signal is reproduced at a half recording speed and the circuit 47 applies the result of decision of the ''1/2 state'' to a PLL32. The value of an output signal PLCK of the PLL32 is equal to the bit rate fCH/2 of the reproduced NRZ signal, and the NRZ signal and the PLCK signal are subject to phase locking. Thus, the capture range of the PLL32 is shifted.</p> |
