| 摘要 |
<p>PURPOSE:To prevent an unstable clock signal from being generated at clock switching by setting independently a selection signal between a high speed clock and a lock speed clock and a clock oscillating control signal. CONSTITUTION:Data (DB0, DB1) in 2-bit are given to a data bus of a memory from a CPU and latched to flip-flops (FF) 4, 5. When the level of both the FFs is '0', both an oscillation control signal 12 and a clock selection signal 31 go to zero,an oscillation circuit 1 is stopped and a low speed clock 22 is selected by a clock switching circuit 3. In bringing the level of the DB0 to logical '1', the oscillation control signal 12 is logical '1' via the FF5 and the oscillation circuit 1 of high speed clock starts operation. After the time for stabilizing oscillation is elapsed, the DB1 is brought into logical '1', then the clock selection signal 31 goes to logical '1' via the FF4 and the clock switch circuit 3 selects the high speed clock 13.</p> |
