| 摘要 |
PURPOSE:To improve the latch-up resistance remarkably by a method wherein the other conductive layer is provided not only on the side but also on the lower part of one conductive island region. CONSTITUTION:Island regions 22, 23 are formed on an n-type (one conductive type) semiconductor substrate 21 and then another n-type island regions 24 is formed in the region 23. The region 23 becomes a p-type impurity layer 25 encircling the region 24. A p-channel MOS-FET and an n-channel MOS-FET are respectively formed in the regions 24 and 22 to complete a C-MOS-FET. When sufficiently positive external noise voltage is impressed on an output terminal VOUT or an input terminal VIN, the connection between base and emitter of a parasitic transistor utilizing a drain region 26 of the p-channel MOS-FET or p<+> type region 29 for connecting gate, the region 24 and the layer 25 respec tively as an emitter, a base and a collector is normally biased while a hole reaching the region 22 is extremely small. Resultantly the current amplification degree of grounding emitter may be reduced remarkable while improving the latch-up resistance. |
