| 摘要 |
PURPOSE:To allow a CPU to perform DAT operation by using TLB optionally even during TLB invalidation processing by IPTE by saving the logical address and actual address of an entry to be invalidated when a DAT request is made. CONSTITUTION:When a dynamic address conversion DAT request is generated during the TLB invalidation processing for page table entry invalidation IPTE, the logical address and actual address to be invalidated are saved in stand-by addresses respectively, the IPTE is interrupted temporarily, and information showing that the IPTE is in process is held. The TLB and its peripheral circuits become usable, so the TLB is referred to for the DAT and the logical address as an object of DAT is compared with the saved logical address to be invalidated; when both logical addresses are not coincident with each other and the entry of the logical address of the TLB coincident with the logical address as the object of DAT is effective, the actual address of this entry is regarded as the actual address of a DAT result.
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