| 摘要 |
PURPOSE:To decrease the number of components by storing a flag in advance in the least significant bit, applying repetitively subtraction until the flag is outputted from a register when a divisor is subtracted from a dividend to eliminate a counter control section. CONSTITUTION:A sign flag 1 is set to the least significant bit of a quotient register 9 at the initial state of a divider. When a subtraction for division is executed by a subtractor 3, a subtraction propriety signal outputted from the subtractor 3 is inputted serially to the quotient register 9 as a quotient bit Q1. The sign flag 1 set to the least significant bit so far is shifted by the 2nd bit. The subtractor 3 subtracts the divisor from the dividend sequentially and quotient bits Q2-Q4 are inputted sequentially to the quotient register 9 at each subtraction. The sign flag 1 is shifted by 1 bit sequentially attended with the subtraction. When a quotient bit Q4 is outputted from the subtractor 3, the sign flag 1 is outputted from the most significant bit of the quotient register 9, given to the subtractor 3 to complete the subtraction. |
