| 摘要 |
PURPOSE:To intermit the execution of a program at plural stop addresses by writing in advance an interruption signal to a desired address corresponding to a stop address location of the program among an address of a RAM. CONSTITUTION:In order to set a stop address of a program by a CPU1, an address signal 17 is outputted to set ROM selection signal 18a, b and a data signal 16, and an interruption signal is written to an address corresponding to any stop address of address brake RAMs 11, 12. Further, the signal 17 is used to set a gate selection signal 18c and the signal 16 and a gate signal 19c. Then the state is in the stop address signal detection wait state. A debug program is executed by the CPU1 and when the signal 17 is coincident with the stop address, an interruption signal is read from the RAM11 or 12. Then the signal is latched by a circuit 14a, and becomes an interruption signal 19a for the CPU1. The CPU1 sets a selection signal 18d to recognize the interruption signal and reports the occurrence of an event. |
