发明名称 MEMORY DEVICE
摘要 PURPOSE:To simplify the constitution of a control circuit and to improve both the reliability and the maintenance properties, by securing such constitution where a refresh action is started by the 1st refresh start circuit when the 2nd clock is set in a continuous clock mode and said refresh action is switched by the 2nd refresh start circuit in a single clock mode respectively. CONSTITUTION:In a continuous clock mode the accesses produced from an access control circuit 4 are sent to a timing generating circuit 5 in the form of a start signal G0, an operator signal OPE, an address signal AD and a write signal WD respectively. A timing generating circuit 5 receives the signal G0 and starts a timing chain consisting of flip-flops FF10-16. The signal OPE is decoded by decoder DEC40, and the action modes for read R0, write WO and refresh RFO are set to FF18-20 respectively. In a read/write action mode a column address strobe RAS and a row address strobe CAS are turned on in the cycles T1 and T2 respectively and then turned off in the cycles T5 and T6.
申请公布号 JPS61145796(A) 申请公布日期 1986.07.03
申请号 JP19840267914 申请日期 1984.12.19
申请人 FUJITSU LTD 发明人 IKEHARA SHOHEI
分类号 G11C11/401;G11C11/34;G11C29/00;G11C29/12;G11C29/56 主分类号 G11C11/401
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