| 摘要 |
<p>Register-modelled radio system comprising a plurality of register-modelled processors having the addressable registers (240) for modelling the virtual state of the processor; a serial bus (230) interconnecting the register-modelled processors for communicating between the addressable registers; and a communications protocol (310) for passing said information to or from said addressable registers (240), whereby the virtual state of said radio portion may be determined or altered by, respectively, communicating information from or to said addressable register means (240). The communications protocol (310) further comprises information packet having an address, an operation code, optional data, and an error detection device, such as a cyclical redundancy check packet. The operation code is chosen from the group of primitive operations codes reset, read, write, bit set, bit clear; ackowledge, and negative acknowledge.</p> |
