发明名称 DECODER FOR RUN LENGTH LIMITED CODE
摘要 PURPOSE:To attain miniaturization by dividing n bits into plural blocks, decoding each divided block tentatively and decoding a data word based on the combination of the results to decrease the capacity of a ROM. CONSTITUTION:A recovered code word is stored in the unit of code words in an S/P converter 1 and a 12-bit D flip-flop 2. The head bit of a code word is given to one input of an exclusive OR gate 4 via an inverter 3. Further, the 3rd-6th bits and the head bit of the 2nd block are given to the other input. The 4 bits relating to the 1st block are fed to a ROM5 among the outputs of the gate 4 to output a 2-bit value R1. Then the head bit of the 2nd block is given to one input of an exclusive OR gate 6. Further, the 2nd-6th bits of the 2nd block are fed to the other input. Then a 5-bit bit pattern is fed to a ROM7 to output a 3-bit value R2. In giving the tentatively decoded values R1, R2 to a ROM8, a decoded value corresponding to the R1, R2 is outputted.
申请公布号 JPS61145935(A) 申请公布日期 1986.07.03
申请号 JP19840269108 申请日期 1984.12.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IKETANI AKIRA
分类号 H03M7/14;G11B20/14;H03M7/46;H04L25/49 主分类号 H03M7/14
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