| 摘要 |
PURPOSE:To attain a stable ternary output by increasing the sum of absolute values of threshold voltages of P and N-channel MOSFETs more than the sum of absolute values of power supply voltage. CONSTITUTION:A P-channel MOSFET11 and an N-channel MOSFET12 are connected in series between a power line with a voltage VDD and a common lin0 to form a complementary MOS circuit. Gates of both the FETs 11, 12 are used together as an input terminal 15, to which an input voltage VIN is given. A series connection point between both the FETs 11, 12 is used as an output terminal 16, from which an output voltage VOUT is extracted, and resistors 13, 14 are connected respectively between the terminal 16 and the power line and between the common line and the terminal 16. The sum of the absolute values of threshold voltages VTP and VTH of both the FETs 11, 12 is larger than the absolute values of the power supply voltage VDD. On the other hand, the resistance value of the resistors 13, 14 is sufficiently larger than the resistance value when the FETs 11, 12 are conductive and sufficiently smaller than the resistance at non-conduction. Thus, a ternary logical circuit in which 6V, 0V, 3V, for example, correspond respectively to logical 1, 0 and the 3rd logical value is obtained.
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