| 摘要 |
PURPOSE:To decrease remarkably code errors due to noise by generating plural clocks during one clock of a digital reproducing signal, using the clock to sample the digital reproducing signal and waveform-shape and using a binary value having the most value among n sets of sample values during one bit period as the value of the said one bit period. CONSTITUTION:A clock reproducing PLL2 reproduces a clock of a frequency n.fr phase-locked to a digital reproducing signal, where fr is a frequency of the basic clock of the digital reproducing signal and the clock is fed to a sift register 1. The shift register 4 uses the clock of frequency nfr, samples sequentially n values in one clock period of the signal and transmits the result sequentially. Then the sampled and stored values are transmitted to a majority decision circuit 3. The circuit 3 outputs 0 when 0s are more in the transmitted n-sample and outputs 1 when 1s are more. Thus, n-sample is obtained during one clock of the digital reproducing signal. When the noise width during one clock is [n/2]/n clock width or below, no code error takes place. |
