发明名称 |
Semiconductor memory incorporating a test pattern generator. |
摘要 |
<p>In a semiconductor device comprising a memory cell array and a test pattern generating circuit, the test pattern generating circuit generates the test pattern and transmits the test pattern to the memory cell array when receiving the least significant bit signal of address signals supplied to the memory cell array and the control signal.</p> |
申请公布号 |
EP0186459(A2) |
申请公布日期 |
1986.07.02 |
申请号 |
EP19850309305 |
申请日期 |
1985.12.20 |
申请人 |
FUJITSU LIMITED |
发明人 |
NAITOH, MITSUGU;SUEHIRO, YOSHIYUKI |
分类号 |
G06F11/22;G01R31/28;G06F15/78;G11C11/401;G11C29/10;G11C29/12;G11C29/46;(IPC1-7):G11C29/00 |
主分类号 |
G06F11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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