| 摘要 |
PURPOSE:To prevent latchup by a method wherein high-concentration impurity- diffused layers are provided in opposing locations of chip regions or in locations out-side a chip region and the layers are biased on a proper power source level. CONSTITUTION:An N<+> layer 41 is provided between regions A, B equivalent to chips and a bias voltage VDD>0 is applied thereto. Application of a surge to a P<+> layer 29 from a pad 42 results in the flow through a substrate 27 of a base current i1 of a parasitic PNP element 33 through an N<+> layer 25 biased with the voltageeVDD, which results in a collector current i2 allowing latchup to easily take place. Insertion of an N<+> layer 41 moderates the potential gradient within the N-base of a parasitic lateral PNP element, reducing the current gain in the element 33 and thereby preventing latchup. In case of a P type substrate, the substrate is biased on a power source VSS level by using the P<+> layer 41. |
