发明名称 SEMICONDUCTOR MEMORY AND MANUFACTURE THEREOF
摘要 PURPOSE:To enable a metallic layer to form without the use of a mask by a method wherein MISFET and a capacity element are constituted connecting with the metallic layer which is provided so as to bury a concave section on a substrate between the above-stated two elements. CONSTITUTION:MISFETQ, which constitutes a memory cell, is formed by a gate insulated film 4, a gate electrode 5 and a semiconductor region 6. A capacity element which constitutes the memory cell, is constituted of a P<+> type region 7, an insulated film 8 and a conductive layer 9. These region 6 and layer 9 are connected by a conductive layer 11, which is provided so as to bury a concave section between FETQ and the capacity element. The layer 11 is provided on the region 6 which is prescribed a side wall 10 formed by self- alignment and the layer 9. A metallic layer obtained by bias-spattering technique is used to the layer 11. Since the layer 11 can be formed without the use of a mask, masking process is unnecessary and manufacturing process is simplified.
申请公布号 JPS61144864(A) 申请公布日期 1986.07.02
申请号 JP19840266180 申请日期 1984.12.19
申请人 HITACHI LTD 发明人 KATSUTO HISAO
分类号 H01L27/10;H01L21/8242;H01L27/108 主分类号 H01L27/10
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