SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

摘要

PURPOSE:To enhance IC device integration by a method wherein useless area is eliminated by organizing a resistance element and MISFET, belonging to a static breakdown preventing circuit constituting an input buffer circuit, and an output transistor constituting an output buffer circuit into one and the same pattern. CONSTITUTION:In a p<-> well 8 provided with an insulating layer 9 on an n<-> type Si substrate 7, an n<+> layer 12 is formed, and a p<+> layer 13 is provided on the n<-> type Si substrate 7. A conductive layer 11 is provided with he intermediary of an insulating film, and an n-channel and p-channel FETs Qn and Qp are built. An FTE wherein Qn1, Qn4, Qn5 and Qn2, Qn3, Qn6 are parallelly connected, a static breakdown preventing circuit 15 consisting of a resistance element concurrently serving as an n<+>-drain 12, and an input stage 16 consisting of Qn7 and Qp constitute an input buffer. Or, in a different wiring design, Qn1, Qn2, Qn3 and Qn4, Qn5, Qn6 are parallelly connected and, in this case, an output buffer is constituted of an FET17 with a low ON resistance and an output stage 18 including Qn7 and Qp. A plurality of such input/output buffers 3 are arranged in the vicinity of an IC1, corresponding to external input/output terminals 2. They are wired in a process wherein wirings are completed for the constitution of logical circuits. In this design, IC integration may be enhanced.