| 摘要 |
PURPOSE:To prevent the appearance of an erroneous data by detecting a coding start point of an input coded data, generating the data while matching the timing of a load/shift instruction signal in the operating clock and using both the signals so as to control a 2-bit shift register. CONSTITUTION:When a composite start code is found out in code bits C1-C7, a control circuit 4 generates a reset signal F and gives an output to a clock generating circuit 5. The circuit 5 frequency-divides the load/shift instruction signal and a 3F clock inputted externally in synchronizing with the signal F to generate a 1F clock signal and gives it to the 2-bit shift register 3. The 2-bit shift register 3 holds the signals X, Y converted by the load/shift instruction signal at D1 and D0 and outputs a 2-bit data held by a 1F clock signal as a serially consecutive NRZ data.
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