发明名称 REFRESH CONTROLLING CIRCUIT OF DYNAMIC RANDOM ACCESS MEMORY
摘要 PURPOSE:To make competing circuit unnecessary and make perfect refreshing possible by dividing a D-RAM into two and making access alternately by the lowermost bit of an address line. CONSTITUTION:A D-RAM is divided into two to form banks A, B. When a microprocessor 1 accesses an address N and designates the bank A, a switching unit 9 selects an address bus 3, and a switching unit 10 selects a refresh address line 7 of the bank B, and D-RAM11 of the bank A is accessed and D-RAM12 of the bank B is refreshed. When an address N+1 is accessed, the switching unit 9 selects a refresh address line 6 of the bank A, and the switching unit 10 selects the bus 3, and the RAM11 is refreshed and RAM12 is accessed.
申请公布号 JPS61144794(A) 申请公布日期 1986.07.02
申请号 JP19840266976 申请日期 1984.12.18
申请人 MITSUBISHI ELECTRIC CORP 发明人 NASU SHOGO
分类号 G11C11/406;G11C11/34 主分类号 G11C11/406
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