| 摘要 |
PURPOSE:To reduce the resistance presented by signal lines for the purpose of improving the gate circuit margin by a method wherein the signal lines constituting a wired OR circuit are formed in an Al multilayer structure wherein through-holes for short-circuiting are provided at appropriate intervals. CONSTITUTION:In a process for constructing a wired OR circuit for four gate circuits G1-G4 separated from each other, the first step is to designate a circuit cell whose internal resistance is to serve as the common terminal resistance for the circuits G1-G4. Suppose the internal resistanceR0 of the gate circuit G3 has been designated as such. Signal lines l1-l3 to connect the G3 circuit output end with the circuits G1, G2, and G4 are formed, making use of pre-arranged channels, of afirst Al layer constituting the lateral component and of a second Al layer the longitudinal component. When the line length or the resistance exceeds a prescribed dimension, an upper layer wiring AL2 is placed over a lower layer wiring AL1 and through-holes TH1 and TH2 are provided, with an appropriate separation between time, for the short-circuiting of the upper and lower layers. In this design, the gate circuit operating margin may be improved and more freedom is ensured in selecting the wiring layout and the gate circuit to be used. |
