发明名称 |
Low power shift register latch |
摘要 |
A combination of logic circuits perform logical operations on data and include a plurality of shift register latches. Each shift register latch includes a latch means for the storing of data, an isolation means for isolating the latch means from data and clock signals connected logic circuits when the isolation means is at a first state, and for conducting data to the latch means when the isolation means is at a second state. Each shift register latch also includes a power reduction means for reducing the power consumed by the isolation means and the latch means.
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申请公布号 |
US4598214(A) |
申请公布日期 |
1986.07.01 |
申请号 |
US19830547524 |
申请日期 |
1983.10.31 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SEXTON, JOE F. |
分类号 |
G11C19/00;G11C19/28;H03K19/00;H03K19/096;(IPC1-7):G11C11/40 |
主分类号 |
G11C19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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