| 摘要 |
PURPOSE:To cope with complication due to the increase in bit number and significance of logic of each bit by constituting a serial data decoding circuit with a counter, a RAM, a logical operating means, a rewrite means and an addressable latch. CONSTITUTION:A counter 34 is operated corresponding to logical significance of each bit of an incoming data and address information is fed to a RAM38 and the addressable latch 54. When the RAM38 receives the address information, the data corresponding to the address is read at each bit and gives an output to a logical operating means. The initial value of the content of the RAM38 is set to a rewrite means. The logical operating means receives the incoming data and the data read out of the RAM38, applies logical operation to the data at each bit and outputs the result. The rewrite means updates the content of the designated address at each bit based on the output of the logical operating means. The addressable latch 54 receives the final content of the RAM when the data incoming is finished, it is latched by address information and outputted. |
