发明名称 CALL DETECTION DELAY SYSTEM
摘要 PURPOSE:To avoid useless repetition of call detection even when a processing- disabled state continues by providing a means for displaying the state of call processing unconsecution of a processing unit and a means for inverting the last look when the state is detected. CONSTITUTION:A line state detection circuit 1 scans a line L and records its state on a line state display circuit 2. The recording and the state of a last look holding circuit 3 are compared at a period of (c) in a figure. When the processing unit 5 is in the processing-disable state to a call detection signal at a point of time t1 in (d) in the figure, a flag display (f) is generated in a call delay flag 6 and a last loop inverting circuit 7 supervises it. That is, when a flag display exists at times T0, T1 during the supervised period of (g) in the figure, the stored content of the last loop holding circuit 3 is inverted as shown in the (b) in the figure. Then a dissidence detection circuit 4 gives a call detection signal to the processing unit 5 at a point of time t4.
申请公布号 JPS61142897(A) 申请公布日期 1986.06.30
申请号 JP19840265687 申请日期 1984.12.17
申请人 FUJITSU LTD 发明人 HIGUCHI MAMORU;UEKI KOHEI;NODA MICHITAKA
分类号 H04Q3/72;(IPC1-7):H04Q3/72 主分类号 H04Q3/72
代理机构 代理人
主权项
地址
您可能感兴趣的专利