发明名称 MANUFACTURE OF MOS SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To contrive to improve the mass production and reliability of a MOS semiconductor integrated circuit device by a method wherein an Si3N4 film, a polycrystalline Si layer and low-impurity concentration diffusion layers are formed in a wiring form and after an oxidation is performed at the specified temperature using the diffusion layers as masks to form an oxide film on the sides of the gate electrode wiring layer, high-impurity concentration diffusion layers are formed. CONSTITUTION:Field oxide films 12 are selectively formed on a P-type single crystal silicon substrate 11 and after a gate oxide film 13 is formed and a polycrystalline silicon layer 14 is formed on the gate oxide film 13, an N<+> type impurity is doped and an SiO2N4 film 15 is formed on the polycrystalline silicon layer 14. Parts of the Si2N4 film 15 and the polycrystalline silicon layer 14 are removed by performing an etching according to a photo etching method and a low-concentration phosphorus impurity is ion-implanted to form N<+> type diffusion layers 16. Then, a wet oxidation is performed at low temperature of 950 deg.C or less using the Si3N4 films 16 as masks to selectively form a thick oxide film on the sides of the polycrystalline silicon wiring layer, an implantation of phosphorus is performed from the polycrystalline silicon wiring layers and the sides thereof in the concentration stronger than that of the N<+>-diffusion layers 16 and N<+> type diffusion layers are formed. After the Si3N4 film 15 is removed by performing an etching, a CVDPSG film 19 is formed and after an annealing is performed, a contact hole is formed, and after that, Al wiring layers 20 are formed.
申请公布号 JPS61141183(A) 申请公布日期 1986.06.28
申请号 JP19840263932 申请日期 1984.12.14
申请人 SEIKO EPSON CORP 发明人 ICHIKAWA MATSUO
分类号 H01L29/78 主分类号 H01L29/78
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