发明名称 PHASE CORRECTING CIRCUIT
摘要 PURPOSE:To correct uncertainty of phase between a decoded signal and its clock signal by outputting a signal from which a unique word pattern is detected in two decoded biphase signals as a correct signal. CONSTITUTION:A timing signal 2 having a period T/2 extracted from a biphase coding signal 1 is divided into two by a frequency division circuit 3 in the burst TDMA system and clock signals 4, 5 having a phase difference T/2 are outputted. The signal 1 is set DFF6, 7 by using the signals 4, 5 to output decoded signals 8, 9, which are inputted respectively to unique word UW pattern detecting circuit 12 and delay circuits 10, 11. The phase of the signals 4, 5 and 8, 9 is uncertain at each burst and the circuit 12 outputs signals 13, 14 corresponding to the signals 8, 9 to a switch control circuit 15 while taking a signal where a correct UW pattern exists in the signals 8, 9 as a correct decoding signal. The signals 8, 9 delayed by the operating time of the circuit 12 is inputted to a switch circuit 18, selected by the control signal of the circuit 15 and outputted together with the clock signal.
申请公布号 JPS61141233(A) 申请公布日期 1986.06.28
申请号 JP19840263021 申请日期 1984.12.14
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 YAMAKI MASAAKI;OSHIMA KAZUYOSHI
分类号 H04L7/00;H04L7/04;H04L7/08 主分类号 H04L7/00
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